The configuration loading time is a function of the configuration clock frequency and precision, data width of the configuration interface, and bitstream size. The calculation is broken down into three steps:
1. Calculate the minimum clock frequency based on the nominal clock frequency and subtract any variation from the nominal.
Minimum Clock Frequency = Nominal Clock - Clock Variation
2. Calculate the minimum PROM bandwidth, which is a function of the data bus width, clock frequency, and PROM type. The PROM bandwidth is the minimum clock frequency multiplied by the bus width.
PROM Bandwidth = Minimum Clock Frequency × Bus Width
3. Calculate the first-stage bitstream loading time, which is the minimum PROM bandwidth from step 2 , divided by the first-stage bitstream size as reported by write_bitstream .
Stage 1 Load Time = (Stage 1 Bitstream Size) / (PROM Bandwidth)
The stage 1 bitstream size, reported by write_bitstream , can be read directly from the terminal or from the log file.
The following is a snippet from the write_bitstream log showing the bitstream size for stage 1 in a VU 095 device:
Creating bitstream...
Tandem stage1 bitstream contains 9175424 bits.
Tandem stage2 bitstream contains 277708576 bits.
Writing bitstream ./xilinx_pcie_ip.bit...
These values represent the explicit values of the bitstream stages, whether in one bit file or two. The effects of bitstream compression are reflected in these values.