Implementation Design Overview - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The implementation design consists of a simple PIO example that can accept read and write transactions and respond to requests, as illustrated in This Figure . Source code for the example is provided with the core. For more information about the PIO example design, see Programmed Input/Output: Endpoint Example Design .

Figure 5-2: Implementation Example Design Block Diagram

X-Ref Target - Figure 5-2

pg156_example_design_block_diagram_x12459.jpg