The Configurator example design consists of four high-level blocks:
• Root Port : The UltraScale Devices Gen3 Integrated Block for PCIe core in Root Port configuration.
• Configurator Block : Logical block which interacts with the configuration space of a PCI Express Endpoint device connected to the Root Port.
• Configurator ROM : Read-only memory that sources configuration transactions to the Configurator Block.
• PIO Master : Logical block which interacts with the user logic connected to the Endpoint by exchanging data packets and checking the validity of the received data. The data packets are limited to a single DWORD and represent the type of traffic that would be generated by a CPU.
Note: The Configurator Block, Configurator ROM, and Root Port are logically grouped in the RTL code within a wrapper file called the Configurator Wrapper.
The Configurator example design, as delivered, is designed to be used with the PIO Slave example included with AMD Endpoint cores and described in Test Bench . The PIO Master is useful for simple bring-up and debugging, and is an example of how to interact with the Configurator Wrapper. The Configurator example design can be modified to be used with other Endpoints.
This Figure shows the various components of the Configurator example design.
This Figure shows how the blocks are connected in an overall system view.
