The user application must transfer each request to be transmitted on the link to the RQ interface of the integrated block as an independent AXI4-Stream packet. Each packet must start with a descriptor and can have payload data following the descriptor. The descriptor is always 16 bytes long, and must be sent in the first 16 bytes of the request packet. The descriptor is transferred during the first two beats on a 64-bit interface, and in the first beat on a 128-bit or 256-bit interface.
The formats of the descriptor for different request types are illustrated in This Figure through This Figure . The format of This Figure applies when the request TLP being transferred is a memory read/write request, an I/O read/write request, or an Atomic Operation request. The format in This Figure is used for Configuration Requests. The format in This Figure is used for Vendor-Defined Messages (Type 0 or Type 1) only. The format in This Figure is used for all ATS messages (Invalid Request, Invalid Completion, Page Request, PRG Response). For all other messages, the descriptor takes the format shown in This Figure .
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X-Ref Target - Figure 3-44 
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Table: Requester Request Descriptor Fields describes the individual fields of the completer request descriptor.
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Bit Index |
Field Name |
Description |
|---|---|---|
|
1:0 |
Address Type |
This field is defined for memory transactions and Atomic Operations only. The integrated block copies this field into the AT of the TL header of the request TLP. • 00: Address in the request is untranslated • 01: Transaction is a Translation Request • 10: Address in the request is a translated address • 11: Reserved |
|
63:2 |
Address |
This field applies to memory, I/O, and Atomic Op requests. This is the address of the first Dword referenced by the request. The user application must also set the First_BE and Last_BE bits in s_axis_rq_tuser to indicate the valid bytes in the first and last Dwords, respectively. When the transaction specifies a 32-bit address, bits [63:32] of this field must be set to 0. |
|
74:64 |
Dword Count |
These 11 bits indicate the size of the block (in Dwords) to be read or written (for messages, size of the message payload). The valid range for Memory Write Requests is 0-256 Dwords. Memory Read Requests have a valid range of 1-1024 Dwords. For I/O accesses, the Dword count is always 1. For a zero length memory read/write request, the Dword count must be 1, with the First_BE bits set to all zeros. The integrated block does not check the setting of this field against the actual length of the payload supplied (for requests with payload), nor against the maximum payload size or read request size settings of the integrated block. |
|
78:75 |
Request Type |
Identifies the transaction type. The transaction types and their encodings are listed in Table: Transaction Types . |
|
79 |
Poisoned Request |
This bit can be used to poison the request TLP being sent. This feature is supported on all request types except Type 0 and Type 1 Configuration Write Requests. This bit must be set to 0 for all requests, except when the user application detects an error in the block of data following the descriptor and wants to communicate this information using the Data Poisoning feature of PCI Express. This feature is supported on all request types except Type 0 and Type 1 Configuration Write Requests. |
|
87:80 |
Requester Function/Device Number |
Device and/or Function number of the Requester Function. Endpoint mode: • ARI enabled: ° Bits [87:80] must be set to the Requester Function number. • ARI disabled: ° Bits [82:80] must be set to the Requester Function number. ° Bits [87:83] are not used Upstream Port for Switch use case (Endpoint mode is selected within the IP): • ARI enabled: ° Bits [87:80] must be set to the Requester Function number. • ARI disabled: ° Bits [82:80] must be set to the Requester Function number. ° Bits [87:83] are not used if the request is originating from the switch itself. These bits must be set to the Requester Device number where the request was originated if the switch is relaying the request (Requester is external to the switch). This is used in conjunction with Requester ID Enable bit in the descriptor. Root Port mode (Downstream Port): • ARI enabled: ° Bits [87:80] must be set to the Requester Function number. • ARI disabled: ° Bits [87:80] must be set to the Requester Function number. ° Bits [87:83] must be set to the Requester Device number. This is used in conjunction with Requester ID Enable bit in the descriptor. |
|
95:88 |
Requester Bus Number |
Bus number associated with the Requester Function. Endpoint mode: • Not used Upstream Port for Switch use case (Endpoint mode is selected within the IP): • Not used if the request is originating from the switch itself. These bits must be set to the Requester Bus number where the request was originated if the switch is relaying the request (Requester is external to the switch). This is used in conjunction with Requester ID Enable bit in the descriptor. Root Port mode (Downstream Port): • Must be set to the Requester Bus number. This is used in conjunction with Requester ID Enable bit in the descriptor. |
|
103:96 |
Tag |
PCIe Tag associated with the request. For Non-Posted transactions, the integrated block uses the value from this field if the AXISTEN_IF_ENABLE_CLIENT_TAG parameter is set (that is, when tag management is performed by the user application). Bits [101:96] are used as the tag. Bits [103:102] are reserved. If this parameter is not set, tag management logic in the integrated block generates the tag to be used, and the value in the tag field of the descriptor is not used. |
|
119:104 |
Completer ID |
This field is applicable only to Configuration requests and messages routed by ID. For these requests, this field specifies the PCI Completer ID associated with the request (these 16 bits are divided into an 8-bit bus number, 5-bit device number, and 3-bit function number in the legacy interpretation mode. In the ARI mode, these 16 bits are treated as an 8-bit bus number + 8-bit Function number.). |
|
120 |
Requester ID Enable |
1’b1: The client supplies Bus, Device, and Function numbers in the descriptor to be populated as the Requester ID field in the TLP header. 1’b0: IP uses Bus and Device numbers captured from received Configuration requests and the client supplies Function numbers in the descriptor to be populated as the Requester ID field in the TLP header. Endpoint mode: • Must be set to 1’b0. Upstream Port for Switch use case (Endpoint mode is selected within the IP): • Set to 1’b0 when the request is originating from the switch itself. • Set to 1’b1 when the switch is relaying the request (Requester is external to the switch). This is used in conjunction with Requester Bus Number bits [95:88] and Requester Function/Device Number bits [87:83] when ARI is not enabled. Root Port mode: • Must be set to 1’b1. This is used in conjunction with Requester Bus Number bits [95:88] and Requester Function/Device Number bits [87:83] when ARI is not enabled. |
|
123:121 |
Transaction Class (TC) |
PCIe Transaction Class (TC) associated with the request. |
|
126:124 |
Attributes |
These bits provide the setting of the Attribute bits associated with the request. Bit 124 is the No Snoop bit and bit 125 is the Relaxed Ordering bit. Bit 126 is the ID-Based Ordering bit, and can be set only for memory requests and messages. The integrated block forces the attribute bits to 0 in the request sent on the link if the corresponding attribute is not enabled in the Function's PCI Express Device Control register. |
|
127 |
Force ECRC |
Force ECRC insertion. Setting this bit to 1 forces the integrated block to append a TLP Digest containing ECRC to the Request TLP, even when ECRC is not enabled for the Function sending request. |
|
15:0 |
Snoop Latency |
This field is defined for LTR messages only. It provides the value of the 16-bit Snoop Latency field in the TLP header of the message. |
|
31:16 |
No-Snoop Latency |
This field is defined for LTR messages only. It provides the value of the 16-bit No-Snoop Latency field in the TLP header of the message. |
|
35:32 |
OBFF Code |
The OBFF Code field is used to distinguish between various OBFF cases: • 1111b: “CPU Active” – System fully active for all device actions including bus mastering and interrupts • 0001b: “OBFF” – System memory path available for device memory read/write bus master activities • 0000b: “Idle” – System in an idle, low power state All other codes are reserved. |
|
111:104 |
Message Code |
This field is defined for all messages. It contains the 8-bit Message Code to be set in the TL header. Appendix F of the PCI Express Base Specification, rev. 3.0 [Ref 2] provides a complete list of the supported Message Codes. |
|
114:112 |
Message Routing |
This field is defined for all messages. The integrated block copies these bits into the 3-bit Routing field r[2:0] of the TLP header of the Request TLP. |
|
15:0 |
Destination ID |
This field applies to Vendor-Defined Messages only. When the message is routed by ID (that is, when the Message Routing field is 010 binary), this field must be set to the Destination ID of the message. |
|
63:32 |
Vendor-Defined Header |
This field applies to Vendor-Defined Messages only. It is copied into Dword 3 of the TLP header. |
|
63:0 |
ATS Header |
This field is applicable to ATS messages only. It contains the bytes that the integrated block copies into Dwords 2 and 3 of the TLP header. |