The GTH transceivers in the Integrated Block for PCI Express (PCIe®) solution support 1-lane, 2-lane, 4-lane, and 8-lane operation, running at 2.5 GT/s (Gen1), 5.0 GT/s (Gen2), and 8.0 GT/s (Gen3) line speeds. Endpoint configurations are supported.
The customer user interface is compliant with the AMBA® AXI4-Stream interface. This interface supports separate Requester, Completion, and Message interfaces. It allows for flexible data alignment and parity checking. Flow control of data is supported in the receive and transmit directions. The transmit direction additionally supports discontinuation of in-progress transactions. Optional back-to-back transactions use straddling to provide greater link bandwidth.
Detailed features of the core are:
• High-performance, highly flexible, scalable, and reliable general-purpose I/O core
° Compliant with the PCI Express Base Specification, rev. 3.0 [Ref 2]
° Compatible with conventional PCI software model
• GTH transceivers
° 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s line speeds
° 1-lane, 2-lane, 4-lane, and 8-lane operation
• Endpoint or Root Port configuration
• Multiple Functions and Single Root I/O Virtualization (SR-IOV) in the Endpoint configuration
° Up to two physical functions
° Up to six virtual functions
• Standardized user interface(s)
° Compliant to AXI4-Stream
° Separate Requester, Completion, and Message interfaces
° Flexible Data Alignment
° Parity generation and checking on AXI4-Stream interfaces
° Easy-to-use packet-based protocol
° Full-duplex communication enabling
° Optional back-to-back transactions to enable greater link bandwidth utilization
° Support for flow control of data and discontinuation of an in-process transaction in transmit direction
° Support for flow control of data in receive direction
• Compliant with PCI and PCI Express power management functions
• Optional Tag Management feature
• Maximum transaction payload of up to 1024 bytes
• End-to-End Cyclic Redundancy Check (ECRC)
• Advanced Error Reporting (AER)
• Multi-Vector MSI for up to 32 vectors and MSI-X
• Atomic operations and Transaction Layer Packets (TLP) processing hints