This section includes information about using AMD tools to customize and generate the core in the Vivado Design Suite.
IMPORTANT: If you are customizing and generating the core in the Vivado IP Integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 15] for detailed information. IP Integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value you can run the validate_bd_design command in the Tcl console.
You can customize the core for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
1. Select the IP from the Vivado IP catalog.
2. Double-click the selected IP, or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 14] , and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 16]
Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE). This layout might vary from the current version.
The Customize IP dialog box for the UltraScale Devices Gen3 Integrated Block for PCIe core consists of two modes: Basic Mode Parameters and Advanced Mode Parameters . To select a mode, use the Mode drop-down list on the first page of the Customize IP dialog box. The following sections explain the parameters available in each of these modes.