Overview - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The main components that enable XVC-over-PCIe debug are as follows:

Host PC XVC-Server application

Host PC PCIe-XVC driver

XVC-over-PCIe enabled FPGA design

These components are provided as a reference on how to create XVC connectivity for AMD FPGA designs. These three components are shown in This Figure and connect to the Vivado Design Suite debug feature through a TCP/IP socket.

Figure E-1: XVC-over-PCIe Software and Hardware Components

X-Ref Target - Figure E-1

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