G T Locations - 4.4 English

This appendix provides a list of GTs locations available for this IP core and lists some key recommendations that should be considered when selecting the GT location. The following sections include tables that identify which GT Banks are available for selection based on the PCIe block location as selected during IP customization.

• Virtex UltraScale Devices Available GT Quads

• Kintex UltraScale Devices Available GT Quads

A GT Quad is comprised of four GT lanes. When selecting GT Quads for the PCIe IP, AMD recommends that you use the GT Quad most adjacent to the PCIe hard block. While this is not required, it will improve place, route, and timing for the design.

• Link widths of x1, x2, and x4 require one bonded GT Quad and should not split lanes between two GT Quads.

• A link width of x8 requires two adjacent GT Quads that are bonded and are in the same SLR.

PCIe lane 0 is placed in the top-most GT of the top-most GT Quad by default (as shown in Vivado Integrated Design Environment (IDE) Device view). Subsequent lanes use the next available GTs moving vertically down the device as the lane number increments. This means that by default the highest PCIe lane number uses the bottom-most GT in the bottom-most GT Quad that is used for PCIe. During IP customization, you can select the desired GT Quad for PCIe lane 0 from the drop-down selections.

The PCIe reference clock ( sys_clk_p / sys_clk_n ) uses GTREFCLK0 in the PCIe lane 0
GT Quad for x1, x2, x4, and x8 configurations by default. You can modify the reference clock default location by adding pin location constraints to the design.

The following diagrams show the ideal GT Quad and reference clock selections for various PCIe link configurations relative to the PCIe block location for a representative device.

Some PCIe locations have non-ideal GT Quad selections as result of their proximity to the edge of the device, SLR boundary, or other PCIe blocks. In these scenarios, the most adjacent GTs may not be optimal for place and route, but will work as desired. The figure below shows one common example.