Tandem PCIe - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

Tandem PCIe is similar to Tandem PROM. I n th e first s t age bitstream , onl y th e con figuration memo ry cell s tha t a r e necessary for P C I Exp r es s operatio n a r e l o a d e d f r o m th e P R OM . After the stage 1 bitstream is loaded, the PCI Express port is capable of responding to enumeration traffic. S u bseq u e ntl y , th e stage 2 bi t s t r ea m is transmitted through th e PCI Express li n k .

VIDEO: Create a Tandem PCIe Design for the KCU105 explains how to create a Tandem design targeting the KCU105 Evaluation Kit.

This Figure illu s t r a t e s th e bi t s t r eam l o a d in g f l o w .

Figure 3-8: Tandem PCIe Bitstream Load Steps

X-Ref Target - Figure 3-8

pg156_tandem_pcie_bitstream_x12937.jpg

T ande m P C I e i s simila r t o th e s t and a r d mode l use d t oda y i n t e r m s o f t oo l f lo w a n d bi t s t r eam generation . T w o bi t s t r eam s a r e p r o d uce d when running bitstream generation . One BIT file representing the stage 1 i s downl o aded in t o th e PROM while the other BIT file representing the user application (stage 2) configures the rest of the FPGA using the Media Configuration Access Port (MCAP).