The transfer of a message on the CQ interface is similar to
that of a memory write request, except that a payload might not always be present. The
transfer starts with the 128-bit descriptor, followed by the payload, if present. When the
Dword-aligned mode is in use, the payload immediately follows the descriptor. When the
address-alignment mode is in use, the first Dword of the payload is supplied in a new beat
after the descriptor, and always starts in byte lane 0. You can determine the end of the
payload from the states of the m_axis_cq_tlast and
m_axis_cq_tkeep signals. The byte_en signals in
m_axis_cq_tuser also indicate the valid bytes in the payload. The First
Byte Enable and Last Byte Enable bits in m_axis_cq_tuser should not be used
for Message transactions.