xmpu_end_lo15 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

xmpu_end_lo15 (DDRMC_NOC) Register Description

Register Namexmpu_end_lo15
Offset Address0x0000010270
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionXMPU end address, lower portion

xmpu_end_lo15 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_lo31:12rwNormal read/write0x0Lower portion of entries end address
Reserved11:0roRead-only0x0XMPU end address, lower portion