nsu0_err_log0_3 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

nsu0_err_log0_3 (DDRMC_NOC) Register Description

Register Namensu0_err_log0_3
Offset Address0x00000005F0
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionNSU0 non-fatal error log

nsu0_err_log0_3 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_l31:0roRead-only0x0Lowest 32 bits of the AXI address