F0_RDDQ_PQTR_FINAL_6 (DDRMC_LPDDR4_XRAM) Register Description
Register Name | F0_RDDQ_PQTR_FINAL_6 |
Offset Address | 0x0000003364 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | RDDQ Rising Edge Final |
Read DQ Centering calibration stage: Final delay value for rising edge clock. Permuted by nibbles.
F0_RDDQ_PQTR_FINAL_6 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | RDDQ Rising Edge Final |