F0_RDDQ_IDELAY_FINAL_13 (DDRMC_LPDDR4_XRAM) Register Description
Register Name | F0_RDDQ_IDELAY_FINAL_13 |
Offset Address | 0x00000030B0 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | RDDQ Idelay Final |
Read DQ Centering calibration stage: Final Idelay values for each data bit in the read path. Permuted by DQ bits.
F0_RDDQ_IDELAY_FINAL_13 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | RDDQ Idelay Final |