REG_ISR (NOC_NMU) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID

AM019

Release Date

2023-11-17

Revision

1.1

REG_ISR (NOC_NMU) Register Description

Register Name	REG_ISR
Offset Address	0x0000000030
Absolute Address	This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width	32
Type	wtcReadable, write a 1 to clear
Reset Value	0x00000000
Description	Interrupt Status Register

REG_ISR (NOC_NMU) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
mem_clear	28	wtcReadable, write a 1 to clear	0x0	mem clear error
scan_clear	27	wtcReadable, write a 1 to clear	0x0	scan clear error
data_par_wr	26	wtcReadable, write a 1 to clear	0x0	data parity errors (write)
addr_par_wr	25	wtcReadable, write a 1 to clear	0x0	address parity errors (write)
timeout_wr	24	wtcReadable, write a 1 to clear	0x0	various timeout errors (write)
ecc_1bit_wr	23	wtcReadable, write a 1 to clear	0x0	ECC 1-bit error, correctable (write)
ecc_2bit_wr	22	wtcReadable, write a 1 to clear	0x0	ECC 2-bit error, not correctable (write)
npp_in_wr	21	wtcReadable, write a 1 to clear	0x0	NPP and VC map in errors (write)
addr_remap_wr	20	wtcReadable, write a 1 to clear	0x0	address remap multiple matches (write)
addr_map_wr	19	wtcReadable, write a 1 to clear	0x0	address map error, wrong space (write)
xlx_infos_wr	18	wtcReadable, write a 1 to clear	0x0	AXI IF Xilinx rule violation non-fatal (write)
xlx_rules_wr	17	wtcReadable, write a 1 to clear	0x0	AXI IF Xilinx rule violation fatal (write)
axi_rules_wr	16	wtcReadable, write a 1 to clear	0x0	AXI IF AXI rule violation (write)
npp_rpoison	15	wtcReadable, write a 1 to clear	0x0	response data poison (read)
vc_credit_tx	14	wtcReadable, write a 1 to clear	0x0	VC map out credit overflow (net received credits are >15)
vc_credit_rx	13	wtcReadable, write a 1 to clear	0x0	VC map in credit underflow (response flits received is more than the credits sent out)
npp_unexp	12	wtcReadable, write a 1 to clear	0x0	unexpected NPP flit in during clock gating, or NPP flit in to unmapped VC
rrob_chk_rd	11	wtcReadable, write a 1 to clear	0x0	UNUSED
data_par_rd	10	wtcReadable, write a 1 to clear	0x0	UNUSED
addr_par_rd	9	wtcReadable, write a 1 to clear	0x0	address parity errors (read)
timeout_rd	8	wtcReadable, write a 1 to clear	0x0	various timeout errors (read)
ecc_1bit_rd	7	wtcReadable, write a 1 to clear	0x0	ECC 1-bit error, correctable (read)
ecc_2bit_rd	6	wtcReadable, write a 1 to clear	0x0	ECC 2-bit error, not correctable (read)
npp_in_rd	5	wtcReadable, write a 1 to clear	0x0	NPP and VC map in errors (read)
addr_remap_rd	4	wtcReadable, write a 1 to clear	0x0	address remap multiple matches (read)
addr_map_rd	3	wtcReadable, write a 1 to clear	0x0	address map error, wrong space (read)
xlx_infos_rd	2	wtcReadable, write a 1 to clear	0x0	AXI IF Xilinx rule violation non-fatal (read)
xlx_rules_rd	1	wtcReadable, write a 1 to clear	0x0	AXI IF Xilinx rule violation fatal (read)
axi_rules_rd	0	wtcReadable, write a 1 to clear	0x0	AXI IF AXI rule violation (read)