F0_DQSGATE_READ_LAT_FINAL_3 (DDRMC_DDR4_XRAM) Register Description
Register Name | F0_DQSGATE_READ_LAT_FINAL_3 |
Offset Address | 0x00000026F8 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | DQSGate Final Read Latency |
DQS Gate calibration stage: Final Read Latency value. Permuted by byte lanes.
F0_DQSGATE_READ_LAT_FINAL_3 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | DQSGate Final Read Latency |