| Field Name | Bits | Type | Reset Value | Description |
|---|
| EHP33 | 27 | wtcReadable, write a 1 to clear | 0x0 | Correctable ECC error found on an incoming flit |
| PMON_CAP | 26 | wtcReadable, write a 1 to clear | 0x0 | Performance Monitor Capture |
| EHP24 | 24 | wtcReadable, write a 1 to clear | 0x0 | CATTRIP |
| EHP23 | 23 | wtcReadable, write a 1 to clear | 0x0 | HBM Memory detects parity error on command AERR raised by the HBM memory |
| EHP22 | 22 | wtcReadable, write a 1 to clear | 0x0 | XMPU access violation in the transaction |
| EHP21 | 21 | wtcReadable, write a 1 to clear | 0x0 | Parity error detected command FIFO data. The controller goes into an undefined state |
| EHP20 | 20 | wtcReadable, write a 1 to clear | 0x0 | Uncorrectable ECC error found on a header flit. The command and data are dropped in the NPP and no response is sent |
| EHP19 | 19 | wtcReadable, write a 1 to clear | 0x0 | Error raised when HBM controllers NSU egress port receives a credit return when it is not ready to receive (detected during initialization of controller). The HBM controller does not take any action |
| EHP18 | 18 | wtcReadable, write a 1 to clear | 0x0 | Destination ID received with the flit does not match the destination ID of the NSU port. The HBM controller goes into an undefined state |
| EHP17 | 17 | wtcReadable, write a 1 to clear | 0x0 | Error raised when zero credits available on the ingress path, but a flit is still received. The HBM controller goes into an undefined state |
| EHP16 | 16 | wtcReadable, write a 1 to clear | 0x0 | Parity error in either BRESP or the RRESP control signals. If BRESP has error, WRITE bit is set in the log register. Similarly, READ bit is set in the log register if RRESP has the error. The HBM controller goes into an undefined state |
| EHP15 | 15 | wtcReadable, write a 1 to clear | 0x0 | Error raised when a wrap transaction is received with an invalid AxLen. The transaction is dropped. The HBM controller goes into an undefined state |
| EHP14 | 14 | wtcReadable, write a 1 to clear | 0x0 | Triggered when a NoC flit is received on an unconfigured VC. The HBM controller goes into an undefined state |
| EHP13 | 13 | wtcReadable, write a 1 to clear | 0x0 | Error is raised if AXI length on the header flit is greater than 15, or in a write transaction, the number of write data flits does not match the AXI length. The HBM controller goes into an undefined state if either occurs |
| EHP12 | 12 | wtcReadable, write a 1 to clear | 0x0 | A write data flit was received with uncorrectable ECC error. If HBM ECC is enabled, a parity error is injected in the data buffer and the data path then injects a 2 bit ECC error when writing the data to memory. If ECC is disabled, a parity error is injected in the data buffer and the data path then sets all the data masks to disable the write |
| EHP11 | 11 | wtcReadable, write a 1 to clear | 0x0 | Parity error found on data pulled from the asynchronous write data FIFO to forward to the write buffer. If HBM ECC is enabled, a parity error is injected in the data buffer and the data path then injects a 2 bit ECC error when writing the data to memory. If ECC is disabled, a parity error is injected in the data buffer and the data path then sets all the data masks to disable the write |
| EHP10 | 10 | wtcReadable, write a 1 to clear | 0x0 | Parity error found on data pulled from the asynchronous read response FIFO when sending RRESP over NoC. A SLVERR is forced on the outgoing response flit |
| EHP9 | 9 | wtcReadable, write a 1 to clear | 0x0 | NoC data flit arrived with command poison bit set. The NoC switch should never send out a flit with command poison bit set. In case it does, this error will be raised and SLVERR response is sent |
| EHP8 | 8 | wtcReadable, write a 1 to clear | 0x0 | NoC data flit arrived with data poison bit set. The NoC switch should never send out a flit with data poison set. In case it does, this error will be raised |
| EHP7 | 7 | wtcReadable, write a 1 to clear | 0x0 | Parity error is found on data pulled from the write buffer to write to the HBM memory |
| EHP6 | 6 | wtcReadable, write a 1 to clear | 0x0 | First write data parity error was retried, the write retry also produced a parity error. If write retry is disabled, the first parity error will produce EHP6 instead of EHP5 |
| EHP5 | 5 | wtcReadable, write a 1 to clear | 0x0 | First parity error detected on a data written to memory. If write retry is disabled, EHP6 will trigger instead |
| EHP4 | 4 | wtcReadable, write a 1 to clear | 0x0 | Double-bit uncorrectable error detected on read data from the HBM memory and SLVERR is sent to NoC |
| EHP3 | 3 | wtcReadable, write a 1 to clear | 0x0 | Single bit correctable error detected on a read data from the HBM memory |
| EHP2 | 2 | wtcReadable, write a 1 to clear | 0x0 | Parity error encountered on data pulled from read data buffer while sending RRESP and SLVERR is sent to NoC |
| EHP1 | 1 | wtcReadable, write a 1 to clear | 0x0 | First read parity error was encountered and a read retry produced a parity error as well. However, if read retry is disabled, EHP1 is raised for the first parity error itself and SLVERR is sent to NoC |
| EHP0 | 0 | wtcReadable, write a 1 to clear | 0x0 | First parity error encountered on a read from HBM memory. If read retry is disabled, the first parity error is reported by EHP1- in which case EHP0 will never trigger and SLVERR is sent to NoC |