REG_PERF_FLT0_CMP_S0 (NOC_NMU_HBM2E) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_PERF_FLT0_CMP_S0 (NOC_NMU_HBM2E) Register Description

Register NameREG_PERF_FLT0_CMP_S0
Offset Address0x00000008B0
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
Descriptionmonitor filter-0 compare value set 0

REG_PERF_FLT0_CMP_S0 (NOC_NMU_HBM2E) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
axprot31:29rwNormal read/write0x0AxProt
axburst28:27rwNormal read/write0x0AxBurst
axsize_min26:24rwNormal read/write0x0min AxSize
axlen_min23:16rwNormal read/write0x0min AxLen
axid 6:0rwNormal read/write0x0AxID