eccr0_uncorr_err_data_hi (DDRMC_MAIN) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

eccr0_uncorr_err_data_hi (DDRMC_MAIN) Register Description

Register Nameeccr0_uncorr_err_data_hi
Offset Address0x00000010E4
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionUncorrectable ECC error data hi for DDRMC sub-channel 0

eccr0_uncorr_err_data_hi (DDRMC_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ecc_err_data_hi31:0rwNormal read/write0x0Upper 4 bytes of error data indicated by eccr0_uncorr_err_status bits