REG_IMR0 (NOC_NPS) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID

AM019

Release Date

2023-11-17

Revision

1.1

Register Name	REG_IMR0
Offset Address	0x0000000048
Absolute Address	This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width	32
Type	roRead-only
Reset Value	0x000FFFFF
Description	Interrupt Mask Register. This is a read-only location and can be atomically altered by either the IDR or the IER.

Field Name	Bits	Type	Reset Value	Description
SCAN_CLR_ERR	20	roRead-only	0x0	See REG_ISR for description
P3_BUF_OVF_ERR	19	roRead-only	0x1	See REG_ISR for description
P2_BUF_OVF_ERR	18	roRead-only	0x1	See REG_ISR for description
P1_BUF_OVF_ERR	17	roRead-only	0x1	See REG_ISR for description
P0_BUF_OVF_ERR	16	roRead-only	0x1	See REG_ISR for description
P3_CRDT_OVF_ERR	15	roRead-only	0x1	See REG_ISR for description
P2_CRDT_OVF_ERR	14	roRead-only	0x1	See REG_ISR for description
P1_CRDT_OVF_ERR	13	roRead-only	0x1	See REG_ISR for description
P0_CRDT_OVF_ERR	12	roRead-only	0x1	See REG_ISR for description
P3_CRDT_RDY_ERR	11	roRead-only	0x1	See REG_ISR for description
P2_CRDT_RDY_ERR	10	roRead-only	0x1	See REG_ISR for description
P1_CRDT_RDY_ERR	9	roRead-only	0x1	See REG_ISR for description
P0_CRDT_RDY_ERR	8	roRead-only	0x1	See REG_ISR for description
P3_ROUTE_ERR	7	roRead-only	0x1	See REG_ISR for description
P2_ROUTE_ERR	6	roRead-only	0x1	See REG_ISR for description
P1_ROUTE_ERR	5	roRead-only	0x1	See REG_ISR for description
P0_ROUTE_ERR	4	roRead-only	0x1	See REG_ISR for description
P3_PARITY_ERR	3	roRead-only	0x1	See REG_ISR for description
P2_PARITY_ERR	2	roRead-only	0x1	See REG_ISR for description
P1_PARITY_ERR	1	roRead-only	0x1	See REG_ISR for description
P0_PARITY_ERR	0	roRead-only	0x1	See REG_ISR for description