MGCHK_DEF_RD_VREF_1 (DDRMC_LPDDR4_XRAM) Register Description
| Register Name | MGCHK_DEF_RD_VREF_1 |
|---|---|
| Offset Address | 0x0000001FB0 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Read VREF set by Calibration, MSB |
MGCHK_DEF_RD_VREF_1 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Value | 0 | roRead-only | 0x0 | The VREF setting used by calibration for reads, MSB. |