REG_RESP_P2_1_PERF_FLIT_IN (NOC_NPS4) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_RESP_P2_1_PERF_FLIT_IN (NOC_NPS4) Register Description

Register NameREG_RESP_P2_1_PERF_FLIT_IN
Offset Address0x000000024C
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionResponse Port 2 in flit performance counter1

REG_RESP_P2_1_PERF_FLIT_IN (NOC_NPS4) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ovf31rwNormal read/write0x0This bit indicates the performance counter overflowed, when set to 1. The performance counters stop accumulating when this bit is set to 1:
0: No overflow
1: Counter overflow
count130:0rwNormal read/write0x0Count1. This count should be concatenated with Count0 to generate a 63 bit counter value:
{Count1, Count0}