HBMMC_MC_PM_ACTIVATE_PC1 (HBMMC_MC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_MC_PM_ACTIVATE_PC1 (HBMMC_MC) Register Description

Register NameHBMMC_MC_PM_ACTIVATE_PC1
Offset Address0x000000027C
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionPerformance Monitor ACTIVATE Commands Count

HBMMC_MC_PM_ACTIVATE_PC1 (HBMMC_MC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PM_ACTIVATE_CMDS31:0roRead-only0x0Number of DRAM ACTIVATE commands Issued in previous capture window