nsu3_err_log0_2 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

nsu3_err_log0_2 (DDRMC_NOC) Register Description

Register Namensu3_err_log0_2
Offset Address0x0000000688
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionNSU3 non-fatal error log

nsu3_err_log0_2 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
axburst31:30roRead-only0x0AXI burst
01: INCR
10: WRAP
smid29:20roRead-only0x0AXI user ID
axlock19roRead-only0x0AXI LOCK info
0: Normal access
1: Exclusive access
axsize18:16roRead-only0x0AXI size
axlen15:8roRead-only0x0AXI length
npp_ebit 7:0roRead-only0x0ECC corrected NPP error bit