F0_DQSGATE_STG1_RLDLYRANK_FINE_5 (DDRMC_DDR4_XRAM) Register Description
| Register Name | F0_DQSGATE_STG1_RLDLYRANK_FINE_5 |
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| Offset Address | 0x000000239C |
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| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
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| Width | 32 |
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| Type | roRead-only |
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| Reset Value | 0x00000000 |
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| Description | DQSGate Stage 1 RLDelay Rank Fine |
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DQS Gate calibration stage: Fine tap value for the 3rd DQS edge. Permuted by byte lanes and ranks.
F0_DQSGATE_STG1_RLDLYRANK_FINE_5 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| Value | 8:0 | roRead-only | 0x0 | DQSGate Stage 1 RLDelay Rank Fine |