nsu2_perf_mon_ctl_0_0 (DDRMC_NOC) Register Description
| Register Name | nsu2_perf_mon_ctl_0_0 |
|---|---|
| Offset Address | 0x0000000558 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Performance monitor 0 control NSU2 |
nsu2_perf_mon_ctl_0_0 (DDRMC_NOC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| sngl | 1 | rwNormal read/write | 0x0 | This bit controls the enabling of performance counter captures based on mon_en only. If this bit is set to 1 the performance monitoring starts when mon_en is set to 1 , and ends when mon_en is set to 0. The timebase edge is ignored, for performance monitor captures, when this bit is set to 1: 0: disable 1: enable |
| mon_en | 0 | rwNormal read/write | 0x0 | This bit controls the enabling of performance monitor 0. All other control and filter settings should be programmed 1st. This bit should be set to 1 after all other filter and control registers are programmed. Also, this bit should be set to 0 and then 1 for any new filter and control setting to take effect: 0: disable 1: enable |