F0_WRDQDBI_ODLY_DQS_FINAL_8 (DDRMC_DDR4_XRAM) Register Description
Register Name | F0_WRDQDBI_ODLY_DQS_FINAL_8 |
Offset Address | 0x0000003C58 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | WRDQDBI Odelay DQS Final |
Write DQ/DBI Deskew Calibration stage: Final DQS Odelay value. Permuted by byte lanes.
F0_WRDQDBI_ODLY_DQS_FINAL_8 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | WRDQDBI Odelay DQS Final |