dc0_perf_mon_7 (DDRMC_MAIN) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

dc0_perf_mon_7 (DDRMC_MAIN) Register Description

Register Namedc0_perf_mon_7
Offset Address0x00000013E0
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDC monitor 7 channel 0

dc0_perf_mon_7 (DDRMC_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
oh_count_of31rwNormal read/write0x0Accumulator overflow
oh_count30:0rwNormal read/write0x0Number of controller cycles with a non-empty transaction queue without a CAS command in flight on channel 0 in the accumulator period. "in-flight" is defined as the BL/4 controller cycles beginning with the cycle that a CAS command is issued.