HBMMC_TMOD (HBMMC_MC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_TMOD (HBMMC_MC) Register Description

Register NameHBMMC_TMOD
Offset Address0x00000001C8
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x0000000F
DescriptionPOR Last MR to Activate Command Spacing

HBMMC_TMOD (HBMMC_MC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TMOD 9:0rwNormal read/write0xFTime specified in MC clock cycles
Initialization - Minimum time after MRS command to any ROW command