REG_ISR (NOC_NCRB) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)
Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_ISR (NOC_NCRB) Register Description

Register NameREG_ISR
Offset Address0x0000000044
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

REG_ISR (NOC_NCRB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P1_R2W_EB_CAL_ERR28wtcReadable, write a 1 to clear0x0interrupt is set when input port1 detects receive calibration error for read clock to write clock elastic buffer
P1_W2R_EB_CAL_ERR27wtcReadable, write a 1 to clear0x0interrupt is set when input port1 detects receive calibration error for write clock to read clock elastic buffer
P0_R2W_EB_CAL_ERR26wtcReadable, write a 1 to clear0x0interrupt is set when input port0 detects receive calibration error for read clock to write clock elastic buffer
P0_W2R_EB_CAL_ERR25wtcReadable, write a 1 to clear0x0interrupt is set when input port0 detects receive calibration error for write clock to read clock elastic buffer
SCAN_CLR_ERR20wtcReadable, write a 1 to clear0x0interrupt is set when scan clear error is detected
P1_BUF_OVF_ERR17wtcReadable, write a 1 to clear0x0interrupt is set when input port1 detects receive buffer overflow
P0_BUF_OVF_ERR16wtcReadable, write a 1 to clear0x0interrupt is set when input port0 detects receive buffer overflow
P1_CRDT_OVF_ERR13wtcReadable, write a 1 to clear0x0interrupt is set when output port1 detects credit overflow
P0_CRDT_OVF_ERR12wtcReadable, write a 1 to clear0x0interrupt is set when output port0 detects credit overflow
P1_CRDT_RDY_ERR 9wtcReadable, write a 1 to clear0x0interrupt is set when input port1 detects valid asserted when credit_ready is de-asserted
P0_CRDT_RDY_ERR 8wtcReadable, write a 1 to clear0x0interrupt is set when input port0 detects valid asserted when credit_ready is de-asserted
P1_PARITY_ERR 1wtcReadable, write a 1 to clear0x0interrupt is set when output port1 detects a parity error
P0_PARITY_ERR 0wtcReadable, write a 1 to clear0x0interrupt is set when output port0 detects a parity error