REG_P0_CTL (NOC_NPS) Register Description
| Register Name | REG_P0_CTL |
|---|---|
| Offset Address | 0x000000040C |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Port 0 Control |
REG_P0_CTL (NOC_NPS) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| perf_mon_vc_sel | 7:5 | rwNormal read/write | 0x0 | These bits select the virtual channel being monitored when perf_mon_mode bit is set to 0. |
| perf_mon_mode | 4 | rwNormal read/write | 0x0 | Performance monitor mode: 0: use perf_mon_vc_sel bits to select a single virtual channel to monitor. 1: Scan through all 8 virtual channels and sum occupancy of all virtual channels. |
| en_perf_mon | 3 | rwNormal read/write | 0x0 | This be select performance monitoring when set to 1. When set to 0 the value of performace counters are held to when this bit was last set to 1. |
| tb_sel | 2:0 | rwNormal read/write | 0x0 | These bits select the timebase clock. There are 6 timebase clocks to select from. |