HBMMC_MC_PM_SBRF_PC0 (HBMMC_MC) Register Description
| Register Name | HBMMC_MC_PM_SBRF_PC0 |
|---|---|
| Offset Address | 0x0000000230 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Performance Monitor SINGLE BANK REFRESH Commands Count |
HBMMC_MC_PM_SBRF_PC0 (HBMMC_MC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PM_SBRF_CMDS | 31:0 | roRead-only | 0x0 | Number of DRAM single bank refresh commands Issued in previous capture window |