CAL_ERROR_PHY_NIBBLE_8_0 (DDRMC_LPDDR4_XRAM) Register Description
| Register Name | CAL_ERROR_PHY_NIBBLE_8_0 |
|---|---|
| Offset Address | 0x0000000418 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Calibration Error Nibble |
CAL_ERROR_PHY_NIBBLE_8_0 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Value | 8:0 | roRead-only | 0x0 | Indicates which PHY nibbles have an error. Each bit location represents a nibble. [0]=nibble 0, [1]=nibble 1, etc. Nibble numbering corresponds to nibble number in the pin name for the first triplet. Example: IO_L18N_XCC_N6P1_M0P37_700 , N6 is the 6th nibble. For this device, 700,701, 702 is a triplet, and so 700 is the 1st triplet. |