xmpu_end_hi5 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

xmpu_end_hi5 (DDRMC_NOC) Register Description

Register Namexmpu_end_hi5
Offset Address0x0000010184
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionXMPU end address, upper portion

xmpu_end_hi5 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0Register bits [15:0] correspond to end address bits [47:32]
addr_hi15:0rwNormal read/write0x0Register bits [15:0] correspond to end address bits [47:32]