HBMMC_TRP (HBMMC_MC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_TRP (HBMMC_MC) Register Description

Register NameHBMMC_TRP
Offset Address0x0000000130
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000015
DescriptionTRP

HBMMC_TRP (HBMMC_MC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TRP 5:0rwNormal read/write0x15Time specified in HBM clock cycles. Minimum Precharge to Activate to same bank