REG_IMR2 (NOC_NSU) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID

AM019

Release Date

2023-11-17

Revision

1.1

Register Name	REG_IMR2
Offset Address	0x0000000060
Absolute Address	This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width	32
Type	roRead-only
Reset Value	0x003FFFFF
Description	Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.

Field Name	Bits	Type	Reset Value	Description
scan_clr_err	21	roRead-only	0x1	Scan clear error
wpoison_wr	20	roRead-only	0x1	wpoison detection from NPP packet
addr_par_wr	19	roRead-only	0x1	address parity errors (write)
timeout_wr	18	roRead-only	0x1	various timeout errors (write)
ecc_1bit_wr	17	roRead-only	0x1	ECC 1-bit error, correctable (write)
ecc_2bit_wr	16	roRead-only	0x1	ECC 2-bit error, not correctable (write)
npp_in_wr	15	roRead-only	0x1	NPP and VC map in errors (write)
xlx_infos_wr	14	roRead-only	0x1	AXI IF Xilinx rule violation non-fatal (write)
xlx_rules_wr	13	roRead-only	0x1	AXI IF Xilinx rule violation fatal (write)
axi_rules_wr	12	roRead-only	0x1	AXI IF AXI rule violation (write)
vc_credit_tx	11	roRead-only	0x1	VC map out credit overflow (net received credits are >15)
vc_credit_rx	10	roRead-only	0x1	VC map in credit underflow (response flits received is more than the credits sent out)
unexpected	9	roRead-only	0x1	unexpected behavior - unexpected packet in the channel
data_par_rd	8	roRead-only	0x1	data parity errors (read)
addr_par_rd	7	roRead-only	0x1	address parity errors (read)
timeout_rd	6	roRead-only	0x1	various timeout errors (read)
ecc_1bit_rd	5	roRead-only	0x1	ECC 1-bit error, correctable (read)
ecc_2bit_rd	4	roRead-only	0x1	ECC 2-bit error, not correctable (read)
npp_in_rd	3	roRead-only	0x1	NPP and VC map in errors (read)
xlx_infos_rd	2	roRead-only	0x1	AXI IF Xilinx rule violation non-fatal (read)
xlx_rules_rd	1	roRead-only	0x1	AXI IF Xilinx rule violation fatal (read)
axi_rules_rd	0	roRead-only	0x1	AXI IF AXI rule violation (read)