REG_10 (CMT_XPLL) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID: AM019
Release Date: 2023-11-17
Revision: 1.1

REG_10 (CMT_XPLL) Register Description

Register Name	REG_10
Offset Address	0x0000000050
Absolute Address	This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000A00
Description	REG_10

REG_10 (CMT_XPLL) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:16	razRead as zero	0x0	for prediv2
CLKOUT3_P5_FEDGE	15	rwNormal read/write	0x0	for prediv2
CLKOUT3_START_H	14	rwNormal read/write	0x0	for prediv2
CLKOUT3_P5EN	13	rwNormal read/write	0x0	for prediv2
clkout3_USED	12	rwNormal read/write	0x0	TRUE: The pre-divide of 2 is enabled
CLKOUT3_PREDIV2	11	rwNormal read/write	0x1	TRUE: The pre-divide of 2 is enabled
CLKOUT3_MX	10:9	rwNormal read/write	0x1	XPLL O3 counter clock input mux control
CLKOUT3_EDGE	8	rwNormal read/write	0x0	XPLL O3 counter high to low clock edge transition control
CLKOUT3_DT	7:0	rwNormal read/write	0x0	XPLL O3 counter delay setting