dc_add_par_err_log1_0 (DDRMC_MAIN) Register Description
| Register Name | dc_add_par_err_log1_0 |
|---|---|
| Offset Address | 0x0000001394 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Channel 0 DC address parity error log1 |
dc_add_par_err_log1_0 (DDRMC_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| err_log_info | 31:0 | rwNormal read/write | 0x0 | Channel 0 Final Arbiter error log info (bit [22:0]) and RETRY error log info (bit [31:23]) [4:0]: transaction entry ID (RAOM or WRRA) [9:5]: transaction QOS [10]: scrub [11]: RMW [12]: RAW [17:13]: RAW ID [22:18]: Read Reorder Buffer address [29:23]: retry state [30]: retry FIFO empty [31]: retry address parity fatal error The retry state bits in the log registers are not going to change exactly with the RETRY FSM. The "dc_add_par_err_log1_0_err_log_info" register logs twice: 1) the first time when the farb detects the error [31:23] (from retry buffer) and [22:0] (from farb block) are logged 2) the second time when the DRAM asserts an alert_n, [31:23] (from retry buffer) and [22:0] (from farb block) are logged |