nsu3_perf_filter_0_0 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

nsu3_perf_filter_0_0 (DDRMC_NOC) Register Description

Register Namensu3_perf_filter_0_0
Offset Address0x00000005A0
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance monitor filter set 0 NSU3

nsu3_perf_filter_0_0 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
axlock29rwNormal read/write0x0AxLock
axprot28:26rwNormal read/write0x0AxProt
axburst25:24rwNormal read/write0x0AxBurst
axlen_max23:20rwNormal read/write0x0Maximum AxLen
axlen_min19:16rwNormal read/write0x0Minimum AxLen
axid15:0rwNormal read/write0x0AxID