F0_DB_MREP_MRD_LAT_35 (DDRMC_DDR4_XRAM) Register Description
Register Name | F0_DB_MREP_MRD_LAT_35 |
Offset Address | 0x00000049C4 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Data Buffer Read Latency |
LRDIMM Data Buffer Read Calibration Stage: MRD latency and MREP phase. Permuted by nibbles and ranks.
F0_DB_MREP_MRD_LAT_35 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
mrd_latency | 8:6 | roRead-only | 0x0 | MRD Latency |
mrep_phase | 5:0 | roRead-only | 0x0 | MREP Phase |