na_err_ctrl_1 (DDRMC_NOC) Register Description
| Register Name | na_err_ctrl_1 |
|---|---|
| Offset Address | 0x0000000714 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Flips corresponding egress ECC and/or parity bit. |
na_err_ctrl_1 (DDRMC_NOC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| p3_bew_d_par_done | 31 | rwNormal read/write | 0x0 | Best Effort Write data parity injection done for port 3: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p2_bew_d_par_done | 30 | rwNormal read/write | 0x0 | Best Effort Write data parity injection done for port 2: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p1_bew_d_par_done | 29 | rwNormal read/write | 0x0 | Best Effort Write data parity injection done for port 1: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p0_bew_d_par_done | 28 | rwNormal read/write | 0x0 | Best Effort Write data parity injection done for port 0: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p3_bew_h_par_done | 27 | rwNormal read/write | 0x0 | Best Effort Write command parity injection done for port 3: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p2_bew_h_par_done | 26 | rwNormal read/write | 0x0 | Best Effort Write command parity injection done for port 2: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p1_bew_h_par_done | 25 | rwNormal read/write | 0x0 | Best Effort Write command parity injection done for port 1: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p0_bew_h_par_done | 24 | rwNormal read/write | 0x0 | Best Effort Write command parity injection done for port 0: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p3_isw_d_par_done | 23 | rwNormal read/write | 0x0 | Isochronous Write data parity injection done for port 3: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p2_isw_d_par_done | 22 | rwNormal read/write | 0x0 | Isochronous Write data parity injection done for port 2: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p1_isw_d_par_done | 21 | rwNormal read/write | 0x0 | Isochronous Write data parity injection done for port 1: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p0_isw_d_par_done | 20 | rwNormal read/write | 0x0 | Isochronous Write data parity injection done for port 0: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p3_isw_h_par_done | 19 | rwNormal read/write | 0x0 | Isochronous Write command parity injection done for ports 3: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p2_isw_h_par_done | 18 | rwNormal read/write | 0x0 | Isochronous Write command parity injection done for ports 2: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p1_isw_h_par_done | 17 | rwNormal read/write | 0x0 | Isochronous Write command parity injection done for ports 1: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| p0_isw_h_par_done | 16 | rwNormal read/write | 0x0 | Isochronous Write command parity injection done for ports 0: HW will set the corresponding port bit when one error is injected in non-persistent mode. In persistent mode HW will also set these bits to indicate one or more errors have been injected. |
| inject_bew_d_par | 15:12 | rwNormal read/write | 0x0 | Parity error injection enable for port 0 to 3 of Best Effort Write class data. SW should clear EN and DONE before setting EN again to enable another single injection in non-persistent mode. In persistent mode errors are injected whenever EN is set. 0: Injection disabled 1: Injection enabled |
| inject_bew_h_par | 11:8 | rwNormal read/write | 0x0 | Parity error injection enable for port 0 to 3 of Best Effort Write class (DRAM Controller command). SW should clear EN and DONE before setting EN again to enable another single injection in non-persistent mode. In persistent mode errors are injected whenever EN is set. 0: Injection disabled 1: Injection enabled |
| inject_isw_d_par | 7:4 | rwNormal read/write | 0x0 | Parity error injection enable for port 0 to 3 of Isochronous Write class data. SW should clear EN and DONE before setting EN again to enable another single injection in non-persistent mode. In persistent mode errors are injected whenever EN is set. 0: Injection disabled 1: Injection enabled |
| inject_isw_h_par | 3:0 | rwNormal read/write | 0x0 | Parity error injection enable for port 0 to 3 of Isochronous Write class (DRAM Controller command). SW should clear EN and DONE before setting EN again to enable another single injection in non-persistent mode. In persistent mode errors are injected whenever EN is set. 0: Injection disabled 1: Injection enabled |