F0_DQSGATE_STG1_READ_LAT_28 (DDRMC_DDR4_XRAM) Register Description
| Register Name | F0_DQSGATE_STG1_READ_LAT_28 |
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| Offset Address | 0x00000021B8 |
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| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
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| Width | 32 |
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| Type | roRead-only |
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| Reset Value | 0x00000000 |
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| Description | DQSGate Stage 1 Read Latency |
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DQS Gate calibration stage: Read Latency value after centering on the noise region. Permuted by byte lanes and ranks.
F0_DQSGATE_STG1_READ_LAT_28 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| Value | 8:0 | roRead-only | 0x0 | DQSGate Stage 1 Read Latency |