dc0_perf_mon_3 (DDRMC_MAIN) Register Description
| Register Name | dc0_perf_mon_3 |
|---|---|
| Offset Address | 0x00000013D0 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DC monitor 3 channel 0 |
dc0_perf_mon_3 (DDRMC_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| pre_count_of | 31 | rwNormal read/write | 0x0 | Accumulator overflow |
| pre_count | 30:0 | rwNormal read/write | 0x0 | Number of Precharge commands on channel 0 in the accumulator period, not include Precharge command issued by Refresh Block under LPDDR4 Per-Bank Refresh Mode |