HBMMC_NA1_NA_WR_ECC_ERR_LOG_EHP12 (HBMMC_NA1) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_NA1_NA_WR_ECC_ERR_LOG_EHP12 (HBMMC_NA1) Register Description

Register NameHBMMC_NA1_NA_WR_ECC_ERR_LOG_EHP12
Offset Address0x00000001D4
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionECC Error on Rx-ed Data Flit between NMU and NA.

HBMMC_NA1_NA_WR_ECC_ERR_LOG_EHP12 (HBMMC_NA1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PORT121rwNormal read/write0x0If set indicates that error occurred on NPP Port1, else error occurred on Port0
TAG20:13rwNormal read/write0x0Logs the TAG of the transaction
SRC_ID12:1rwNormal read/write0x0Logs the SOURCE ID of the transaction
ERR_VALID 0rwNormal read/write0x0If set indicates a write data flit was received with uncorrectable ECC error