LPQDQSOSCTRACK_WLDLYRNK1_FINE_5 (DDRMC_LPDDR4_XRAM) Register Description
| Register Name | LPQDQSOSCTRACK_WLDLYRNK1_FINE_5 |
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| Offset Address | 0x0000004A0C |
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| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
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| Width | 32 |
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| Type | roRead-only |
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| Reset Value | 0x00000000 |
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| Description | LP4 Oscillator Tracking, Rank 1 Fine Taps |
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Current fine tap setting for each nibble for Rank 1. Permuted by nibbles.
LPQDQSOSCTRACK_WLDLYRNK1_FINE_5 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| Value | 8:0 | roRead-only | 0x0 | LP4 Oscillator Tracking, Rank 1 Fine Taps |