REG_IOR (HBMMC_NA0) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_IOR (HBMMC_NA0) Register Description

Register NameREG_IOR
Offset Address0x0000000030
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000005
DescriptionInterrupt Offset Register. 5-bit offset for the interrupt mapping is provided by this register.

REG_IOR (HBMMC_NA0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
OFFSET 4:0rwNormal read/write0x5Determines which of the 2 of the 20 bits of the interrupt line in the npi protocol interface gets raised when an interrupt occurs. At value 0, the lowest 2 bits are assigned. At value 1, the 2nd and 3rd lowest bits are assigned. Each increment by one moves the bits assigned by one.