reg_config0 (DDRMC_MAIN) Register Description
| Register Name | reg_config0 |
|---|---|
| Offset Address | 0x0000000258 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | General memory controller configuration |
reg_config0 (DDRMC_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| width_per_ch | 19:18 | rwNormal read/write | 0x0 | Width of each DDR Data Bus on each channel, not counting ECC bits. Must be programmed consistently with the reg_pinout register. 0x0: 64 - Only valid for DDR4 in single channel mode. 0x1: 32 0x2: 16 |
| num_ch | 17 | rwNormal read/write | 0x0 | Number of independent DDR DRAM Command/Address/Data Channels. Must be programmed consistently with reg_pinout register. 0: 1 channel 1: 2 channels |
| num_ranks | 15:14 | rwNormal read/write | 0x0 | 0x0: 1 0x1: 2 0x2: 4 |
| dram_size | 10:8 | rwNormal read/write | 0x0 | 0x0: 4G 0x1: 6G 0x2: 8G 0x3: 12G 0x4: 16G 0x5: 32G |