eccr1_corr_err_data_lo (DDRMC_MAIN) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

eccr1_corr_err_data_lo (DDRMC_MAIN) Register Description

Register Nameeccr1_corr_err_data_lo
Offset Address0x0000001100
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCorrectable ECC error data low for DDRMC sub-channel 1

eccr1_corr_err_data_lo (DDRMC_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ecc_err_data_low31:0rwNormal read/write0x0Lowest 4 bytes of error data indicated by eccr1_corr_err_status bits