HBMMC_MC_PM_EN (HBMMC_MC) Register Description
| Register Name | HBMMC_MC_PM_EN |
|---|---|
| Offset Address | 0x00000001E8 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Performance Monitor Capture Mode |
HBMMC_MC_PM_EN (HBMMC_MC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PM_CAP_CNT_EXT | 15:8 | rwNormal read/write | 0x0 | Upper 8 bits (bit 39-32) of capture window count, in NPI clocks |
| PM_FILTER_EN | 4 | rwNormal read/write | 0x0 | 0 - MC Performance monitor includes all operations 1 - MC Performance monitor includes only operations matching filter set for corresponding NPP port |
| PM_SAMP_EXT | 3 | rwNormal read/write | 0x0 | 1- Event status returns [47:32] value 0 - Event status returns [31:0] value |
| PM_CAP_MODE | 2:1 | rwNormal read/write | 0x0 | 00 - Continuous Capture Updates every capture period 01 - One shot accumulate capture over capture period starting at PM_EN 10 - Once shot accumulate capture over capture period starting at PM_EN and 1st BL4 operation received in scheduler 11 - Reserved |
| PM_EN | 0 | rwNormal read/write | 0x0 | 0 - MC Performance monitor disabled 1 - MC Performance monitor enabled |