F0_WRDQDBI_STG2_DQS_ODLY_16 (DDRMC_DDR4_XRAM) Register Description
Register Name | F0_WRDQDBI_STG2_DQS_ODLY_16 |
Offset Address | 0x0000003490 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | WRDQDBI Stage 2 DQS Odelay |
Write DQ/DBI Deskew Calibration stage: Odelay for DQS after reverting. Permuted by byte lanes.
F0_WRDQDBI_STG2_DQS_ODLY_16 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | WRDQDBI Stage 2 DQS Odelay |